Research and development of a gamma-ray imaging spectrometer in the MeV range in Barcelona

Copyright 2010 Society of Photo-Optical Instrumentation Engineers (SPIE). One print or electronic copy may be made for personal use only. Systematic electronic or print reproduction and distribution, duplication of any material in this paper for a fee or for commercial purposes, or modification of the content of the paper are prohibited.Gamma-ray astrophysics in the MeV energy range plays an important role for the understanding of cosmic explosions and acceleration mechanisms in a variety of galactic and extragalactic sources, e.g., Supernovae, Classical Novae, Supernova Remnants (SNRs), Gamma-Ray Bursts (GRBs), Pulsars, Active Galactic Nuclei (AGN). Through the development of focusing telescopes in the MeV energy range, it will be possible to reach unprecedented sensitivities, compared with those of the currently operating gamma ray telescopes. In order to achieve the needed performance, a detector with mm spatial resolution and very high peak efficiency is required. It will be also desirable that the detector could detect polarization of the source. Our research and development activities in Barcelona aim to study a gamma-ray imaging spectrometer in the MeV range suited for the focal plane of a gamma-ray telescope mission, based on CdTe pixel detectors arranged in multiple layers with increasing thicknesses, to enhance gamma-ray absorption in the Compton regime. We have developed an initial prototype based on several CdTe module detectors, with 11x11 pixels, a pixel pitch of 1mm and a thickness of 2mm. Each pixel is stud-bump bonded to a fanout board and routed to a readout ASIC to measure pixel position, pulse height and rise time information for each incident gamma-ray photon. We will report on the results of an optimization study based on simulations, to select the optimal thickness of each CdTe detector within the module to get the best energy resolution of the spectrometer.Peer reviewe

Mapping the depleted area of silicon diodes using a micro-focused X-ray beam

For the Phase-II Upgrade of the ATLAS detector at CERN, the current ATLAS Inner Detector will be replaced with the ATLAS Inner Tracker (ITk). The ITk will be an all-silicon detector, consisting of a pixel tracker and a strip tracker. Sensors for the ITk strip tracker are required to have a low leakage current up to bias voltages of -500 V to maintain a low noise and power dissipation. In order to minimise sensor leakage currents, particularly in the high-radiation environment inside the ATLAS detector, sensors are foreseen to be operated at low temperatures and to be manufactured from wafers with a high bulk resistivity of several kΩ·cm. Simulations showed the electric field inside sensors with high bulk resistivity to extend towards the sensor edge, which could lead to increased surface currents for narrow dicing edges. In order to map the electric field inside biased silicon sensors with high bulk resistivity, three diodes from ATLAS silicon strip sensor prototype wafers were studied with a monochromatic, micro-focused X-ray beam at the Diamond Light Source (Didcot, U.K.). For all devices under investigation, the electric field inside the diode was mapped and its dependence on the applied bias voltage was studied.Individual authors1 were supported in part by the U.S. Department of Energy under Contract No. DE-AC02-05CH11231. The work at SCIPP4 was supported by the Department of Energy, grant DE-SC0010107. This work5 issupported and financed in part by the Spanish Ministry of Science, Innovation and Universities through the Particle Physics National Program, ref. FPA2015-65652-C4-4-R (MICINN/FEDER, UE), and co-financed with FEDER funds

Sistema digital para realizar biopsia estereotáxica

Referencia OEPM: P200401878 .-- Fecha de solicitud: 29/07/2004.-- Titulares: Udiat Centre Diagnostic, S.A., Institut de Fisica d'Altes Enerties (IFAE), Consejo Superior de Investigaciones Científicas (CSIC).Sistema digital para realizar biopsias estereotáxicas con una aguja de biopsia, comprendiendo dicho sistema una serie de dispositivos para: emitir rayos X, detectar y transformar fotones de rayos X en señales eléctricas, posicionar una muestra de tejido entre la fuente de rayos X y el detector, procesar las señales eléctricas y generar imágenes. El sistema bien puede disponer de una serie de dispositivos complementarios a los mencionados, bien puede disponer de unos medios de posicionamiento para situar en dos posiciones los dispositivos mencionados y obtener imágenes según dos orientaciones.Peer reviewe

Transistor de efecto de campo de unión, método de obtención y uso del mismo

Transistor de efecto de campo de unión y método de obtención del mismo. En este documento se detallan tanto un dispositivo transistor de efecto de campo de unión (JFET), objeto de un primer aspecto de la invención, como el método para obtener el mismo, objeto de un segundo aspecto de la invención. El dispositivo transistor de efecto de campo de unión (JFET), presenta una serie de trincheras circulares concéntricas que se encuentran protegidas por una o varias trincheras de protección. Dichas trincheras de protección tienen forma rectangular con esquinas redondeadas y se desdoblan en trincheras de protección flotantes y trincheras de protección polarizadas, tal manera que una trinchera de protección polarizada es exterior a la última trinchera concéntrica mientras que una trinchera de protección flotante es exterior a dicha trinchera de protección polarizada.Peer reviewedConsejo Superior de Investigaciones Científicas (España)A1 Solicitud de adición a la patent

Transistor de efecto de campo de unión, método de obtención y uso del mismo

En este documento se detallan tanto un dispositivo transistor de efecto de campo de unión (JFET), objeto de un primer aspecto de la invención, como el método para obtener el mismo, objeto de un segundo aspecto de la invención. El dispositivo transistor de efecto de campo de unión (JFET), presenta una serie de trincheras circulares concéntricas que se encuentran protegidas por una o varias trincheras de protección. Dichas trincheras de protección tiene forma rectangular con esquinas redondeadas y se desdoblan en trincheras de protección flotantes y trincheras de protección polarizadas, tal manera que una trinchera de protección polarizada es exterior a la última trinchera concéntrica mientras que una trinchera de protección flotante es exterior a dicha trinchera de protección polarizada. [ES]This document describes both a junction field effect-transistor (JFET) device, which is the subject of a first aspect of the invention, and the method for obtaining same, which is the subject of a second aspect of the invention. The junction field-effect transistor (JFET) device has a series of concentric circular trenches that are protected by one or more protective trenches. Said protective trenches are rectangular with rounded corners and are split into floating protective trenches and polarised protective trenches, such that one polarised protective trench is located outside the last concentric trench while one floating protective trench is located outside said polarised protective trench. [EN]Peer reviewedConsejo Superior de Investigaciones Científicas (España)A1 Solicitud de patente con informe sobre el estado de la técnic

Sistema digital para realizar biopsia esterotáxica.

Filing Date: 2005-07-27.--Priority Data: ES P200401878 (2004-07-29)The invention relates to a digital system (1) for performing stereotaxic biopsies with a biopsy needle. The inventive system (1) comprises a series of devices which are used to: emit X-rays, detect and transform X-ray photons into electric signals, position a tissue sample between the X-ray source and the detector, process the electric signals, and generate images. The system can also be equipped with a series of devices complementary to those mentioned above, as well as a means for positioning the aforementioned devices in two positions and obtaining images in two different orientations

Transistor tipo jfet y método de obtención del mismo

[EN] The invention relates to a semiconductor device corresponding to a JFET-type transistor which has a multilayer arrangement of various materials, resulting in a vertical JFET-type transistor, i.e. the current flows from the upper part of the chip (source) to the lower part (drain), crossing the entire silicon block. The invention also relates to a method for producing said JFET device, said method using the DRIE (deep reactive-ion etching) processing technique.[ES] De detalla un dispositivo semiconductor correspondiente a un transistor tipo JFET que presenta una disposición multicapa de varios materiales, dando como resulta de esa disposición un dispositivo transistor tipo JFET vertical; es decir que la corriente fluye desde la parte superior del chip (fuente) hacia la parte inferior (drenaje), atravesando todo el bloque de silicona, mientras que en un segundo de la invención se tiene un método para la fabricación del dispositivo JFET del primer aspecto; método que hace uso de la técnica de procesamiento DRIE (Deep reactive-ion atching).Peer reviewedConsejo Superior de Investigaciones Científicas (España)A1 Solicitud de patente con informe sobre el estado de la técnic

Jfet-type transistor and method for the production thereof

[ES] De detalla un dispositivo semiconductor correspondiente a un transistor tipo JFET que presenta una disposición multicapa de varios materiales, dando como resulta de esa disposición un dispositivo transistor tipo JFET vertical; es decir que la corriente fluye desde la parte superior del chip (fuente) hacia la parte inferior (drenaje), atravesando todo el bloque de silicona, mientras que en un segundo de la invención se tiene un método para la fabricación del dispositivo JFET del primer aspecto; método que hace uso de la técnica de procesamiento DRIE (Deep reactive-ion atching).[EN] The invention relates to a semiconductor device corresponding to a JFET-type transistor which has a multilayer arrangement of various materials, resulting in a vertical JFET-type transistor, i.e. the current flows from the upper part of the chip (source) to the lower part (drain), crossing the entire silicon block. The invention also relates to a method for producing said JFET device, said method using the DRIE (deep reactive-ion etching) processing technique.Peer reviewedConsejo Superior de Investigaciones Científicas (España)B1 Patente sin examen previ

Jfet-type transistor and method for the production thereof

[ES] De detalla un dispositivo semiconductor correspondiente a un transistor tipo JFET que presenta una disposición multicapa de varios materiales, dando como resulta de esa disposición un dispositivo transistor tipo JFET vertical; es decir que la corriente fluye desde la parte superior del chip (fuente) hacia la parte inferior (drenaje), atravesando todo el bloque de silicona, mientras que en un segundo de la invención se tiene un método para la fabricación del dispositivo JFET del primer aspecto; método que hace uso de la técnica de procesamiento DRIE (Deep reactive-ion atching).[EN] The invention relates to a semiconductor device corresponding to a JFET-type transistor which has a multilayer arrangement of various materials, resulting in a vertical JFET-type transistor, i.e. the current flows from the upper part of the chip (source) to the lower part (drain), crossing the entire silicon block. The invention also relates to a method for producing said JFET device, said method using the DRIE (deep reactive-ion etching) processing technique.Peer reviewedConsejo Superior de Investigaciones Científicas (España)A1 Solicitud de patente con informe sobre el estado de la técnic

A New Vertical JFET Power Device for Harsh Radiation Environments

An increasing demand for power electronic devices able to be operative in harsh radiation environments is now taking place. Specifically, in High Energy Physics experiments the required power devices are expected to withstand very high radiation levels which are normally too hard for most of the available commercial solutions. In this context, a new vertical junction field effect transistor (JFET) has been designed and fabricated at the Instituto de Microelectrónica de Barcelona, Centro Nacional de Microelectrónica (IMB-CNM, CSIC). The new silicon V-JFET devices draw upon a deep-trenched technology to achieve volume conduction and low switch-off voltage, together with a moderately high voltage capability. The first batches of V-JFET prototypes have been already fabricated at the IMB-CNM clean room, and several aspects of their design, fabrication and the outcome of their characterization are summarized and discussed in this paper. Radiation hardness of the fabricated transistors have been tested both with gamma and neutron irradiations, and the results are also included in the contribution.The authors would like to heartily thank the Clean Room staff of the IMB-CNM for their dedicated work and kind availability. This work is supported and financed in part by the Spanish Ministry of Economy and Competitiveness through the Particle Physics National Program, ref. FPA2014-55295-C3-2-R and FPA2015-65652-C4-4-R (MINECO/FEDER, UE), and co-financed with FEDER funds and the European Union’s Horizon 2020 research and innovation programme under grant agreement No. 654158. The work is also partially supported by the Generalitat de Catalunya (2014-SGR-1596). The authors want to thank Pedro Valdivieso and co-workers at NAYADE facility (CIEMAT) and the staff on the TRIGA nuclear reactor facilities (JSI), for their efficiency and dedication in performing the managing and irradiation of our devices.We acknowledge support by the CSIC Open Access Publication Initiative through its Unit of Information Resources for Research (URICI)